1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same.
2. Description of the Related Art
Recently, micropatterning of CMOS devices advances scaling in the vertical (height) direction in accordance with that in the horizontal (width) direction. This shallows source/drain regions (deep junctions) and increases the junction leakage. Therefore, Ni silicide which consumes a small amount of silicon must be used in the formation of a silicide.
In the fabrication process of this CMOS device, a metal to be used as an interconnection is finally deposited and patterned by lithography in order to form a metal interconnection. In this lithography, alignment with an underlying pattern is performed using an optical method. This alignment with the underlying pattern uses an alignment mark formed in a region of the underlying pattern.
Unfortunately, Ni silicide is formed in this alignment mark region, and a heating step after the formation of the Ni silicide roughens the surface of the Ni silicide. When the alignment with the underlying pattern is performed using an optical method, this surface roughness acts as noise and significantly decreases the alignment accuracy.
Note that Jpn. Pat. Appln. KOKAI Publication No. 2001-307999 discloses an invention which prevents the formation of a silicide by forming a protective film on an alignment mark. Jpn. Pat. Appln. KOKAI Publication No. 7-29854 discloses an invention which forms an alignment mark by using a contact hole and buries W by forming WSi in only the contact bottom portion. Jpn. Pat. Appln. KOKAI Publication No. 2001-36036 discloses an invention which uses, as an alignment mark structure, a structure obtained by forming a gate electrode in a recess of a substrate and forming polysilicon and a silicide on the gate. Jpn. Pat. Appln. KOKAI Publication No. 2001-102440 discloses an invention which deposits polysilicon and a silicide on a stepped element isolation portion serving as an alignment mark and then removes the polysilicon and silicide. Jpn. Pat. Appln. KOKAI Publication No. 2002-110500 discloses an invention in which an alignment mark made of a silicide defines the relationship between a distance L from the sidewall of an opening to the alignment mark and a thickness H of an insulating film formed on the upper surface of an alignment layer.